What is L2 cache?
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What is L2 cache?

 

Dear CPU Scorekeeper

I would like to know more about the on-die L2 cache.
  1. Is it an alternative solution to the SRAM cache implementation?
  2. Which CPU's currently use the on-die L2 cache?
  3. Which CPUs currently use the SRAM cache?
  4. Are on-die caches cheaper to make than SRAM chips?
  5. As the fabrication process is reduced to 0.18 and smaller, will the on-die L2 cache be the future of caches on CPU's?
- - Se, October 1999

See the questionCPU Scorekeeper Responds

  1. YES.
  2. Intel's Celeron-A (300MHz and up) and mobile (not desktop) Pentium-II;
    AMD's K6-III.
  3. AMD's K6-2 & K6-III.
  4. NO.
  5. YES (IMHO).

There are currently three flavours of L2 cache employed in today's CPUs. SRAM (Static RAM) cache generally refers to the oldest of the three technologies, where the L2 cache is located on the system motherboard running at the speed of the Front Side Bus (FSB). An on-die L2 cache is a faster alternative to an SRAM cache, particularly as CPU clock speeds continue to increase.

To illustrate the performance impacts of the different types of L2 cache, take these CPUs as an example:

CPU (MHz) on-die L2 (MHz) BSB L2 (MHz) FSB L2 (MHz)
Celeron 300 ***** ***** *****       66
Intel Celeron 300 Performance
Celeron A 300 128 kb x 300 ***** *****       66
Intel Celeron 300A Performance
Celeron A 400 128 kb x 400 ***** *****       66
Intel Celeron 400 Performance
Pentium II 300 ***** 512 kb x 150 *****     100
Intel Pentium II 300 Performance
Pentium II 400 ***** 512 kb x 200 *****     100
Intel Pentium II 400 Performance
K6-2 300 ***** ***** 1024 kb x 100
AMD K6-2 300 Performance
K6-2 400 ***** ***** 1024 kb x 100
AMD K6-2 400 Performance

Intel's Celeron-A's demonstrate the newest implementation of L2 cache: built onto the same die as the CPU itself. Check the Celeron Stats page to see how the transistor count rises dramatically, as a result.

The Pentium-II uses a prior L2 technology, where the cache is built onto a dedicated Back Side Bus (BSB), between the FSB and the CPU. Although the BSB can run at the same speed as the CPU, cache memory capable of such speeds is much more expensive. Therefore, in the Pentium-II, the more economical half-speed cache is used (for a full-speed BSB, check out Intel's Xeon line).

AMD's K6-2 illustrates the oldest, on-board L2 cache design. Though the size of the cache is larger, its FSB speed limit shows its effect as CPU clock speeds increase.

The original Celeron-300, bereft of L2 cache, shows a significant performance penalty as a result. The L2-enabled Celeron-A at 300MHz is able to at least keep pace with a Pentium-II or K6-2 at the same clock speed.

At a processor speed of 400MHz, while its FSB runs at a pokey 66MHz, the Celeron-A still remains in the same performance league as both the Pentium II and the K6-2, mostly due to its newer on-die L2 cache.

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